An oxide Thin Film Transistor (TFT) differs from a conventional amorphous silicon TFT in that a semiconductor layer is made of a metal oxide material, such as Indium Gallium Zinc Oxide (IGZO). The oxide TFT has advantages such as being transparent, insensitive to light, high light intensity, low power consumption and high electron mobility, and thus has been widely used in the industry.
However, for the metal oxide semiconductor layer, the environment condition is highly demanded, and both oxygen gas and steam in the air may adversely affect its characteristics. Thus, an Etch Stop Layer (ESL) is provided on the metal oxide semiconductor layer. As illustrated in FIG. 1, during the production of an oxide TFT array substrate in the related art, a gate electrode 2 and a common electrode line 3 are formed on a substrate 1, and then a gate insulation layer 4 is formed. An oxide semiconductor layer 6 is formed on the gate insulation layer 4, and then an etch stop layer 5 is formed on the substrate 1 on which the oxide semiconductor layer 6 has been formed. A source electrode via hole 8 and a drain electrode via hole 9 are formed and pass through the etch stop layer 5, and a common electrode via hole 10 is formed and passes through the etch stop layer 5 and the gate insulation layer 4, so that the source electrode may be connected to the oxide semiconductor layer 6 through the source electrode via hole 8, the drain electrode may be connected to the oxide semiconductor layer 6 through the drain electrode via hole 9, and the common electrode may be connected to the common electrode line 3 through the common electrode via hole 10. In the related art, the source electrode via hole 8, the drain electrode via hole 9 and the common electrode via hole 10 are formed by a single etching process. It will take a long period of time to form the common electrode via hole 10 by a single etching process, because the via hole 10 is deep and it is required to pass through both the etch stop layer 5 and the gate insulation layer 4. Both the source electrode via hole 8 and the drain electrode via hole 9 only need to pass through the etch stop layer 5 and thus are shallower than the via hole 10. As illustrated in FIG. 1, when it takes a long period of time for the etching process, a portion of the oxide semiconductor layer 6 located at positions corresponding to the source electrode via hole 8 and the drain electrode via hole 9 may be etched off, and further portions of the gate insulation layer 4 located at the positions corresponding to the source electrode via hole 8 and the drain electrode via hole 9 may be etched off. As a result, either the source electrode or the drain electrode may be connected to the gate electrode, resulting in a condition of data line and gate line short (DGS).
In the related art, a further patterning process for the gate insulation layer is usually introduced for solving the above problem. In other words, the gate insulation layer is formed in advance, and a via hole passing through the gate insulation layer is formed at a position corresponding to the common electrode via hole 10. And then, the source electrode via hole 8, the drain electrode via hole 9 and the common electrode via hole 10 passing through the etch stop layer are formed by a single etching process. However, in this way, the number of the patterning processes for the array substrate as well as the production cost thereof will be increased.